View SSD1828Z_5509411.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

i table of contents 1 general description............................................................................................................ ..... 1 2 features ....................................................................................................................... ................. 2 96x64 graphic display with a icon line ......................................................................................... ..... 2 programmable multiplex ratio [16mux - 65mux] ................................................................................. 2 single supply operation, 1.8 v - 3.3v .......................................................................................... ........ 2 low current sleep mode (<1.0ua) ................................................................................................ ....... 2 on-chip voltage generator / external power supply ........................................................................ 2 software selectable 2x / 3x / 4x / 5x on-chip dc-dc converter ..................................................... 2 on-chip oscillator ............................................................................................................. .................... 2 software selectable on-chip bias dividers, with no external capacitors required ...................... 2 hardware pin selectable for 8-bit 6800-series parallel interface, 8-bit 8080-series parallel interface, 3-wire serial peripheral interface or 4-wire serial peripheral interface .......................... 2 programmable 1/4, 1/5, 1/6, 1/7, 1/8, 1/9 bias ratio ........................................................................... .. 2 maximum +12.0v lcd driving output voltage ................................................................................... 2 on-chip 96 x 65 graphic display data ram ....................................................................................... 2 re-mapping of row and column drivers........................................................................................... .2 vertical scrolling............................................................................................................. ....................... 2 display offset control ......................................................................................................... .................. 2 64 levels internal contrast control ............................................................................................ ......... 2 external contrast control ...................................................................................................... ............... 2 maximum 17mhz spi or 15mhz ppi operation.................................................................................... 2 selectable lcd driving voltage temperature coefficients (4 settings) .......................................... 2 3 ordering information ........................................................................................................... ... 2 4 block diagram .................................................................................................................. ........... 3 5 die arrangement ................................................................................................................ ........ 4
ii 6 pin description ................................................................................................................ ............ 8 6.1 res............................................................................................................................ .................. 8 6.2 ps0 ............................................................................................................................ .................. 8 6.3 ps1 ............................................................................................................................ .................. 8 6.4 cs# ............................................................................................................................ .................. 8 6.5 d/c............................................................................................................................ ................... 8 6.6 r/w(wr#)....................................................................................................................... ............. 8 6.7 e(rd#) ......................................................................................................................... ................ 8 6.8 d 0 -d 7 ............................................................................................................................... ............ 9 6.9 v dd ............................................................................................................................... ................ 9 6.10 rv ss ............................................................................................................................... .............. 9 6.11 cv ss ............................................................................................................................... .............. 9 6.12 v ss ............................................................................................................................... ................ 9 6.13 v ci ............................................................................................................................... ................. 9 6.14 v out ............................................................................................................................... ................ 9 6.15 v l5, v l4, v l3 and v l2 ..................................................................................................................... 9 6.16 com0 ? com63 ................................................................................................................... ....... 9 6.17 icons.......................................................................................................................... ................ 9 6.18 seg0 ? seg95................................................................................................................... ....... 10 6.19 cl ............................................................................................................................. ................. 10 6.20 mio ............................................................................................................................ ................ 10 6.21 test0~13....................................................................................................................... ........... 10 6.22 nobump ......................................................................................................................... .......... 10 7 functional block descriptions ........................................................................................ 11 7.1 command decoder and command interface........................................................................ 11 7.2 mpu parallel 6800-series interface ........................................................................................ 11 7.3 mpu parallel 8080-series interface ........................................................................................ 11
iii 7.4 mpu serial 4-wire interface.................................................................................................... .12 7.5 mpu serial 3-wire interface.................................................................................................... .12 7.6 graphic display data ram (gddram).................................................................................. 12 7.7 oscillator circuit ............................................................................................................. ......... 12 7.8 lcd driving voltage generator and regulator .................................................................... 13 7.9 161 bit latch .................................................................................................................. .......... 13 7.10 level selector ................................................................................................................. .......... 13 7.11 hv buffer cell (level shifter)................................................................................................. .13 7.12 default value after hardware reset ........................................................................................ 14 7.13 lcd panel driving waveform ................................................................................................. 14 command table .................................................................................................................. .................. 17 7.14 read status byte ............................................................................................................... ...... 21 7.15 data read / write .............................................................................................................. ....... 21 8 command descriptions .......................................................................................................... 2 2 8.1 set display on/off ............................................................................................................. ...... 22 8.2 set display start line......................................................................................................... ..... 22 8.3 set page address ............................................................................................................... ..... 22 8.4 set higher column address ................................................................................................... 22 8.5 set lower column address.................................................................................................... 22 8.6 set temperature coefficient (tc) value................................................................................ 22 8.7 set segment re-map............................................................................................................. .. 22 8.8 set normal/reverse display ................................................................................................... 22 8.9 set entire display on/off ...................................................................................................... .. 22 8.10 set lcd bias ................................................................................................................... ......... 22 8.11 software reset ................................................................................................................. ........ 23 8.12 set com output scan direction............................................................................................. 23 8.13 set power control register .................................................................................................... 2 3
iv 8.14 set internal regulator resistors ratio.................................................................................. 23 8.15 set contrast control register ................................................................................................ 24 8.16 set frame frequency ............................................................................................................ .... 25 8.17 set multiplex ratio............................................................................................................ ....... 25 8.18 set power save mode............................................................................................................ .. 25 8.19 exit power save mode........................................................................................................... .. 25 8.20 set n-line inversion ........................................................................................................... ...... 25 8.21 exit n-line inversion .......................................................................................................... ...... 25 8.22 set dc-dc converter factor................................................................................................... 25 8.23 set icon enable ................................................................................................................ ........ 25 8.24 start internal oscillator ...................................................................................................... ..... 25 8.25 set display data length........................................................................................................ .. 25 8.26 set test mode .................................................................................................................. ........ 25 8.27 status register read........................................................................................................... ..... 26 extended commands.............................................................................................................. ....... 26 8.28 enable external oscillator input. ............................................................................................ 26 9 maximum ratings ................................................................................................................ ....... 27 10 dc characteristics ............................................................................................................. .... 28 11 ac characteristics ............................................................................................................. .... 30 12 application examples ........................................................................................................... .37
v table of figures figure 1 - block diagram ....................................................................................................... ....................... 3 figure 2 ? ssd1828 pin assignment .............................................................................................. ............. 4 figure 3 ? display data read with the insertion of dummy read ............................................................. 11 figure 4 - oscillator circuitry................................................................................................ ....................... 13 figure 5 - ssd1828 graphic display data ram (gddram) address map (with vertical scroll value 30h) ............................................................................................................................... .............................. 15 figure 6 - lcd display example ?0? ............................................................................................. .............. 16 figure 7 - lcd driving signal from ssd1828..................................................................................... ........ 16 figure 8 - contrast control voltage range curve (v dd =2.775v; v ci =3.5v; tc=-0.05%/ o c) ..................... 24 figure 9 - contrast control flow set segment re-map ............................................................................ .24 figure 10 ? parallel 6800-series interface timing characteristics (ps0 = h, ps1 = h) ............................ 31 figure 11 ? parallel 6800-series interface timing characteristics (ps0 = h, ps1 = h) ............................ 32 figure 12 - parallel 8080-series interface timing characteristics (ps0 = h, ps1 = l) .............................. 33 figure 13 - parallel 8080-series interface timing characteristics (ps0 = h, ps1 = l) .............................. 34 figure 14- serial timing characteristics (ps0 = l) ............................................................................. ....... 35 figure 15 - serial timing characteristics (ps0 = l) ............................................................................ ....... 36 figure 16 - typical application (4-wires spi mode)............................................................................. ....... 37 list of table table 1 - ordering information ................................................................................................. ..................... 2 table 2 - ssd1828 series die pad coordinates ................................................................................... ....... 5 table 3 - ps0 & ps1 interface .................................................................................................. .................... 8 table 4 - v out > v l5 > v l4 > v l3 > v l2 > v ss relationship .............................................................................. 9 table 5 -modes of operation .................................................................................................... .................. 12 table 6 - command table........................................................................................................ .............. 17 table 7 ? extended command table ............................................................................................... .......... 20 table 8 - read status byte ..................................................................................................... .................... 21 table 9 - address increment table.............................................................................................. ............... 21 table 10 - commands required for r/w (wr#) actions on ram ............................................................. 21 table 11 - maximum ratings (voltage referenced to v ss ) ........................................................................ 27 table 12 - dc characteristics (unless otherwise specified, voltage referenced to v ss , v dd = 1.8 to 3.3v, t a = -40 to 85 c)............................................................................................................................. ..... 28 table 13 - ac characteristics (unless otherwise specified, voltage referenced to v ss , v dd = v ci = 2.7v, t a = -40 to 85 c)............................................................................................................................. ..... 30 table 14 ? parallel timing characteristics (t a = -40 to 85 c, v dd = 1.8v, v ss =0v) ................................. 31 table 15 ? parallel timing characteristics (t a = -40 to 85 c, v dd = 2.7, v ss =0v).................................... 32 table 16 - parallel timing characteristics (t a = -40 to 85 c, v dd = 1.8v, v ss =0v) .................................. 33 table 17 - parallel timing characteristics (t a = -40 to 85 c, v dd = 2.7v, v ss =0v) .................................. 34 table 18 ? serial timing characteristics (t a = -40 to 85 c, v dd = 2.7v, v ss =0v) .................................... 35 table 19 ? serial timing characteristics (t a = -40 to 85 c, v dd = 1.8v, v ss =0v) .................................... 36
solomon systech limited solomon systech limited solomon systech limited solomon systech limited semiconductor technical data this document contains information on a new product. specification and information herein are subject to change without notice. copyright ? 2002 solomon systech limited rev 1.10 07/2002 ssd1828 advanced information lcd segment / common driver with controller cmos 1 general description ssd1828 is a single-chip cmos lcd driver with controller for liquid crystal dot-matrix graphic display system. ssd1828 consists of 162 high voltage driving output pins for driving 96 segments, 64 commons and 1 icon driving with dual common outputs. ssd1828 displays data directly from its internal 96x65 bits graphic display data ram (gddram). data/commands are sent from general mcu through hardware selectable 6800-/8080-series compatible parallel interface or 3/4 wires serial peripheral interface. ssd1828 embeds a dc-dc converter, a lcd voltage regulator, an on-chip bias divider and an on-chip oscillator which reduce the number of external components. with the special design on minimizing power consumption and die layout, ssd1828 is suitable for any portable battery-driven applications requiring a long op- eration period and a compact size.
ssd1828 rev 1.10 07/2002 solomon 2 2 features 96x64 graphic display with a icon line programmable multiplex ratio [16mux - 65mux] single supply operation, 1.8 v - 3.3v maximum +12.0v lcd driving output voltage low current sleep mode (<1.0ua) on-chip 96 x 65 graphic display data ram on-chip voltage generator / external power supply on-chip oscillator software selectable on-chip bias dividers, with no external capacitors required hardware pin selectable for 8-bit 6800-series parallel interface, 8-bit 8080-series parallel interface, 3-wire serial peripheral interface or 4-wire serial peripheral interface maximum 17mhz spi or 15mhz ppi operation software selectable 2x / 3x / 4x / 5x on-chip dc-dc converter programmable 1/4, 1/5, 1/6, 1/7, 1/8, 1/9 bias ratio re-mapping of row and column drivers vertical scrolling display offset control 64 levels internal contrast control external contrast control selectable lcd driving voltage temperature coefficients (4 settings) 3 ordering information table 1 - ordering information ordering part number seg com package form SSD1828Z 96 64 + 1 gold bump die
ssd1828 rev 1.10 07/2002 solomon 3 4 block diagram figure 1 - block diagram com0 to com63 test0~13 hv buffer cell level shifter level selector 161 bit latch display timing generator oscillator 96 x 65 bits command decoder command interface parallel / serial interface lcd driving voltage generator 2x / 3x / 4x / 5x dc/dc converter, voltage regulator, bias divider, contrast control, temperature compensation icons seg0~seg95 vout vl5 vl4 vl3 vl2 vss v ci cl v ss v dd d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 (sda) (sck) res# ps0 ps1 cs# d/c r/w e (wr#) (rd#) mio
ssd1828 rev 1.10 07/2002 solomon 4 5 die arrangement figure 2 ? ssd1828 pin assignment die size (with scribe): 9.6 x 1.6 mm 2 die thickness: 53425m bump height: typical 18m bump co-planarity <3m (within die) y pad1 pad123 pad142 pad270 x note: 1. diagram showing the die face up. 2. coordinates are reference to center of the chip. 3. unit of coordinates and size of all alignment marks are in um. 4. all alignment keys do not contain gold bump. test13 test12 test11 mio cl nobump test9 vl5 vl4 vl3 vl2 test8 test7 test6 test5 vout : : vout vss : : vss rvss cvss : : cvss vci : : vci vdd : : vdd d7 (sda) d7 (sda) d6 (sck) d6 (sck) d5 d4 d3 d2 d1 d0 vdd e (rd#) e (rd#) r/w (wr#) r/w (wr#) vss d/c d/c d/c /res vdd /cs /cs vss ps1 vdd vss ps0 vdd test4 test3 test2 test1 vss vss vss vss vss vss vss vss vss nobump vss vss vss vss vss vss vss vss com19 com18 : : : : : : com30 com31 vss vss vss vss com18 com17 com16 : : : : : com0 comsr seg0 seg1 seg2 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : seg94 seg95 com32 com33 com34 : : : : : com43 com44 vss com45 com46 : : : : : : : : com62 com63 icons vss key1 centre: -4227.6, 234 diameter: 80.2 key2 centre: 4203.9, 234 diameter: 80.2 } } } } } 15 x vout 7 x vss 16 x vci 12 x cvss 7 x vdd
ssd1828 rev 1.10 07/2002 solomon 5 table 2 - ssd1828 series die pad coordinates pad # pad name x-pos y-pos pad # pad name x-pos y-pos pad # pad name x-pos y-pos 1 test1 -4199.6 -642.0 51 vci -939.2 -642.0 101 nobump 2344.4 -642.0 2 test2 -4134.8 -642.0 52 vci -874.4 -642.0 102 cl 2409.2 -642.0 3 test3 -4070.0 -642.0 53 vci -809.6 -642.0 103 mio 2474.0 -642.0 4 test4 -4005.2 -642.0 54 vci -744.8 -642.0 104 test11 2564.4 -642.0 5 vdd -3928.7 -642.0 55 vci -680.0 -642.0 105 test12 2629.2 -642.0 6 ps0 -3863.9 -642.0 56 vci -615.2 -642.0 106 test13 2694.0 -642.0 7 vss -3799.1 -642.0 57 cvss -541.7 -642.0 107 vss 2899.2 -702.9 8 vdd -3734.3 -642.0 58 cvss -476.9 -642.0 108 vss 3007.2 -702.9 9 ps1 -3669.5 -642.0 59 cvss -412.1 -642.0 109 vss 3115.2 -702.9 10 vss -3604.7 -642.0 60 cvss -347.3 -642.0 110 vss 3223.2 -702.9 11 /cs -3539.9 -642.0 61 cvss -282.5 -642.0 111 vss 3331.2 -702.9 12 /cs -3475.1 -642.0 62 cvss -217.7 -642.0 112 vss 3439.2 -702.9 13 vdd -3410.3 -642.0 63 cvss -152.9 -642.0 113 vss 3547.2 -702.9 14 /res -3345.5 -642.0 64 cvss -88.1 -642.0 114 nobump 3655.2 -702.9 15 d/c -3280.7 -642.0 65 cvss -23.3 -642.0 115 vss 3763.2 -702.9 16 d/c -3215.9 -642.0 66 cvss 41.6 -642.0 116 vss 3871.2 -702.9 17 d/c -3151.1 -642.0 67 cvss 106.4 -642.0 117 vss 3979.2 -702.9 18 vss -3086.3 -642.0 68 cvss 171.2 -642.0 118 vss 4087.2 -702.9 19 r/w (rw#) -3021.5 -642.0 69 rvss 236.0 -642.0 119 vss 4195.2 -702.9 20 r/w (rw#) -2956.7 -642.0 70 vss 300.8 -642.0 120 vss 4303.2 -702.9 21 e (rd#) -2891.9 -642.0 71 vss 365.6 -642.0 121 vss 4411.2 -702.9 22 e (rd#) -2827.1 -642.0 72 vss 430.4 -642.0 122 vss 4519.2 -702.9 23 vdd -2762.3 -642.0 73 vss 495.2 -642.0 123 vss 4627.2 -702.9 24 d0 -2697.5 -642.0 74 vss 560.0 -642.0 124 vss 4688.1 -564.9 25 d1 -2632.7 -642.0 75 vss 624.8 -642.0 125 vss 4688.1 -456.9 26 d2 -2567.9 -642.0 76 vss 689.6 -642.0 126 vss 4688.1 -348.9 27 d3 -2503.1 -642.0 77 vout 763.1 -642.0 127 vss 4688.1 -240.9 28 d4 -2438.3 -642.0 78 vout 827.9 -642.0 128 com31 4627.2 -139.5 29 d5 -2373.5 -642.0 79 vout 892.7 -642.0 129 com30 4627.2 -74.7 30 d6 (sck) -2308.7 -642.0 80 vout 957.5 -642.0 130 com29 4627.2 -9.9 31 d6 (sck) -2243.9 -642.0 81 vout 1022.3 -642.0 131 com28 4627.2 54.9 32 d7 (sda) -2179.1 -642.0 82 vout 1087.1 -642.0 132 com27 4627.2 119.7 33 d7 (sda) -2114.3 -642.0 83 vout 1151.9 -642.0 133 com26 4627.2 184.5 34 vdd -2049.5 -642.0 84 vout 1216.7 -642.0 134 com25 4627.2 249.3 35 vdd -1984.7 -642.0 85 vout 1281.5 -642.0 135 com24 4627.2 314.1 36 vdd -1919.9 -642.0 86 vout 1346.3 -642.0 136 com23 4627.2 378.9 37 vdd -1855.1 -642.0 87 vout 1411.1 -642.0 137 com22 4627.2 443.7 38 vdd -1790.3 -642.0 88 vout 1475.9 -642.0 138 com21 4627.2 508.5 39 vdd -1725.5 -642.0 89 vout 1540.7 -642.0 139 com20 4627.2 573.3 40 vdd -1660.7 -642.0 90 vout 1605.5 -642.0 140 com19 4627.2 638.1 41 vci -1587.2 -642.0 91 vout 1670.3 -642.0 141 vss 4627.2 702.9 42 vci -1522.4 -642.0 92 test5 1735.1 -642.0 142 com18 4212.0 642.0 43 vci -1457.6 -642.0 93 test6 1799.9 -642.0 143 com17 4147.2 642.0 44 vci -1392.8 -642.0 94 test7 1873.4 -642.0 144 com16 4082.4 642.0 45 vci -1328.0 -642.0 95 test8 1946.9 -642.0 145 com15 4017.6 642.0 46 vci -1263.2 -642.0 96 vl2 2011.7 -642.0 146 com14 3952.8 642.0 47 vci -1198.4 -642.0 97 vl3 2076.5 -642.0 147 com13 3888.0 642.0 48 vci -1133.6 -642.0 98 vl4 2141.3 -642.0 148 com12 3823.2 642.0 49 vci -1068.8 -642.0 99 vl5 2206.1 -642.0 149 com11 3758.4 642.0 50 vci -1004.0 -642.0 100 test9 2270.9 -642.0 150 com10 3564.0 642.0
ssd1828 rev 1.10 07/2002 solomon 6 pad # pad name x-pos y-pos pad # pad name x-pos y-pos 151 com9 3499.2 642.0 201 seg39 259.2 642.0 152 com8 3434.4 642.0 202 seg40 194.4 642.0 153 com7 3369.6 642.0 203 seg41 129.6 642.0 154 com6 3304.8 642.0 204 seg42 64.8 642.0 155 com5 3240.0 642.0 205 seg43 0.0 642.0 156 com4 3175.2 642.0 206 seg44 -64.8 642.0 157 com3 3110.4 642.0 207 seg45 -129.6 642.0 158 com2 3045.6 642.0 208 seg46 -194.4 642.0 159 com1 2980.8 642.0 209 seg47 -259.2 642.0 160 com0 2916.0 642.0 210 seg48 -324.0 642.0 161 icons 2851.2 642.0 211 seg49 -388.8 642.0 162 seg0 2786.4 642.0 212 seg50 -453.6 642.0 163 seg1 2721.6 642.0 213 seg51 -518.4 642.0 164 seg2 2656.8 642.0 214 seg52 -583.2 642.0 165 seg3 2592.0 642.0 215 seg53 -648.0 642.0 166 seg4 2527.2 642.0 216 seg54 -712.8 642.0 167 seg5 2462.4 642.0 217 seg55 -777.6 642.0 168 seg6 2397.6 642.0 218 seg56 -842.4 642.0 169 seg7 2332.8 642.0 219 seg57 -907.2 642.0 170 seg8 2268.0 642.0 220 seg58 -972.0 642.0 171 seg9 2203.2 642.0 221 seg59 -1036.8 642.0 172 seg10 2138.4 642.0 222 seg60 -1101.6 642.0 173 seg11 2073.6 642.0 223 seg61 -1166.4 642.0 174 seg12 2008.8 642.0 224 seg62 -1231.2 642.0 175 seg13 1944.0 642.0 225 seg63 -1296.0 642.0 176 seg14 1879.2 642.0 226 seg64 -1360.8 642.0 177 seg15 1814.4 642.0 227 seg65 -1425.6 642.0 178 seg16 1749.6 642.0 228 seg66 -1490.4 642.0 179 seg17 1684.8 642.0 229 seg67 -1555.2 642.0 180 seg18 1620.0 642.0 230 seg68 -1620.0 642.0 181 seg19 1555.2 642.0 231 seg69 -1684.8 642.0 182 seg20 1490.4 642.0 232 seg70 -1749.6 642.0 183 seg21 1425.6 642.0 233 seg71 -1814.4 642.0 184 seg22 1360.8 642.0 234 seg72 -1879.2 642.0 185 seg23 1296.0 642.0 235 seg73 -1944.0 642.0 186 seg24 1231.2 642.0 236 seg74 -2008.8 642.0 187 seg25 1166.4 642.0 237 seg75 -2073.6 642.0 188 seg26 1101.6 642.0 238 seg76 -2138.4 642.0 189 seg27 1036.8 642.0 239 seg77 -2203.2 642.0 190 seg28 972.0 642.0 240 seg78 -2268.0 642.0 191 seg29 907.2 642.0 241 seg79 -2332.8 642.0 192 seg30 842.4 642.0 242 seg80 -2397.6 642.0 193 seg31 777.6 642.0 243 seg81 -2462.4 642.0 194 seg32 712.8 642.0 244 seg82 -2527.2 642.0 195 seg33 648.0 642.0 245 seg83 -2592.0 642.0 196 seg34 583.2 642.0 246 seg84 -2656.8 642.0 197 seg35 518.4 642.0 247 seg85 -2721.6 642.0 198 seg36 453.6 642.0 248 seg86 -2786.4 642.0 199 seg37 388.8 642.0 249 seg87 -2851.2 642.0 200 seg38 324.0 642.0 250 seg88 -2916.0 642.0
ssd1828 rev 1.10 07/2002 solomon 7 pad # pad name x-pos y-pos 251 seg89 -2980.8 642.0 252 seg90 -3045.6 642.0 253 seg91 -3110.4 642.0 254 seg92 -3175.2 642.0 255 seg93 -3240.0 642.0 256 seg94 -3304.8 642.0 257 seg95 -3369.6 642.0 258 com32 -3434.4 642.0 259 com33 -3499.2 642.0 260 com34 -3564.0 642.0 261 com35 -3628.8 642.0 262 com36 -3693.6 642.0 263 com37 -3758.4 642.0 264 com38 -3823.2 642.0 265 com39 -3888.0 642.0 266 com40 -3952.8 642.0 267 com41 -4017.6 642.0 268 com42 -4082.4 642.0 269 com43 -4147.2 642.0 270 com44 -4212.0 642.0 271 vss -4627.2 702.9 272 com45 -4627.2 638.1 273 com46 -4627.2 573.3 274 com47 -4627.2 508.5 275 com48 -4627.2 443.7 276 com49 -4627.2 378.9 277 com50 -4627.2 314.1 278 com51 -4627.2 249.3 279 com52 -4627.2 184.5 280 com53 -4627.2 119.7 281 com54 -4627.2 54.9 282 com55 -4627.2 -9.9 283 com56 -4627.2 -74.7 284 com57 -4627.2 -139.5 285 com58 -4627.2 -204.3 286 com59 -4627.2 -269.1 287 com60 -4627.2 -333.9 288 com61 -4627.2 -398.7 289 com62 -4627.2 -463.5 290 com63 -4627.2 -528.3 291 icons -4627.2 -593.1 292 vss -4627.2 -702.9 pad123 ss d1 8 2 8 i c x y pad1 pad142 pad270 x y unit remark pad pitch 64.8 64.8 um min. pad space 20.8 20.8 um min. pad # x y unit pad size 1 - 100 44 75 um 101 - - um 102 - 106 44 75 um 107 - 113 75 44 um 114 - - um 115 - 123 75 44 um 124 - 127 44 75 um 128 - 141 75 44 um 142 - 270 44 75 um 271 - 292 75 44 um
ssd1828 rev 1.10 07/2002 solomon 8 6 pin description 6.1 res this pin is reset signal input. when the pin is low, initialization of the chip is executed. 6.2 ps0 this pin pair with ps1 to determine the interface protocol between the driver and mcu. refer to ps1 pin descriptions for more details. 6.3 ps1 this pin pair with ps0 to determine the interface protocol between the driver and mcu, according to the following table. table 3 - ps0 & ps1 interface ps0 ps1 interface l l 3-wire spi (write only) l h 4-wire spi (write only) h l 8080 parallel interface (read and write allowed) h h 6800 parallel interface (read and write allowed) 6.4 cs# this pin is chip select input. the chip is enabled for display data/command transfer only when cs is low. 6.5 d/c this input pin is to identify display data/command cycle. when the pin is high, the data written to the driver will be written into display ram. when the pin is low, the data will be interpreted as command. this pin must be connected to v ss when 3-lines spi interface is used. . 6.6 r/w(wr#) this pin is microprocessor interface signal. when interfacing to a 6800-series microprocessor, the signal indicates read mode when high and write mode when low. when interfacing to an 8080-microprocessor, a data write operation is initiated when r/w(wr) is low and the chip is selected. 6.7 e(rd#) this pin is microprocessor interface signal. when interfacing to an 6800-series microprocessor, a data operation is initiated when e(rd) is high and the chip is selected. when interfacing to an 8080-microprocessor, a data read operation is initiated when e(rd) is low and the chip is selected.
ssd1828 rev 1.10 07/2002 solomon 9 6.8 d 0 -d 7 these pins are 8-bit bi-directional data bus to be connected to the microprocessor?s data bus. when serial mode is selected, d 7 is the serial data input sda and d 6 is the serial clock input sck. 6.9 v dd power supply pin. 6.10 rv ss ground reference of vref. 6.11 cv ss ground reference of analog circuitry. 6.12 v ss ground reference of logic circuitry. 6.13 v ci reference voltage input for internal dc-dc converter. the voltage of generated v cc equals to the multiple factor (2x, 3x, 4x or 5x) times v ci with respect to v ss . note: voltage at this input pin must be larger than or equal to v dd . 6.14 v out this is the most positive voltage supply pin of the chip. it can be supplied externally or generated by the internal regulator. 6.15 v l5, v l4, v l3 and v l2 lcd driving voltages. they can be supplied externally or generated by the internal bias divider. they have the following relationship: v out > v l5 > v l4 > v l3 > v l2 > v ss table 4 - v out > v l5 > v l4 > v l3 > v l2 > v ss relationship 1 : a bias v l5 (a-1)/a * v out v l4 (a-2)/a * v out v l3 2/a * v out v l2 1/a * v out a is equals to 9 at por. 6.16 com0 ? com63 these pins provide the row driving signal com0 - com63 to the lcd panel. see figure 5 or figure 7 about the com signal mapping in different multiplex ratio n. 6.17 icons this pin is the special icons line com signal output.
ssd1828 rev 1.10 07/2002 solomon 10 6.18 seg0 ? seg95 these pins provide the lcd column driving signal. their voltage level is v ss during sleep mode. 6.19 cl this pin is the external clock input for the device, which is enabled by using an extended command. under normal operation, this pin should be left opened and internal oscillator will be used after power on reset. 6.20 mio this pin is used for cascade purpose only. under normal operation, it should be left open. 6.21 test0~13 these pins is used for internal only and should be left open, any connection is not allowed. 6.22 nobump these pins are al metal pads only, without any gold bump on the top. they should be left open, any connection is not allowed.
ssd1828 rev 1.10 07/2002 solomon 11 7 functional block descriptions 7.1 command decoder and command interface this module determines whether the input data is interpreted as data or command. data is directed to this module based upon the input of the d/c pin. if d/c is high, data is written to graphic display data ram (gddram). if d/c is low, the input at d 0 -d 7 is interpreted as a command and it will be decoded and written to the corresponding command register. reset is of the same function as power on reset (por). once res# receives a negative reset pulse of about 1us, all internal circuitry will be back to its initial status. refer to command description section for more information. 7.2 mpu parallel 6800-series interface the parallel interface consists of 8 bi-directional data pins (d 0 - d 7 ), r/w(wr#), d/c, e(rd#) and cs#. r/w(wr#) input high indicates a read operation from the graphic display data ram (gddram) or the status register. r/w(wr#) input low indicates a write operation to display data ram or internal command registers depending on the status of d/c input. the e(rd#) and cs# input serves as data latch signal (clock) when they are high and low respectively. refer to figure 10 of parallel timing characteristics for parallel interface timing diagram of 6800-series microprocessors. in order to match the operating frequency of display ram with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. this is shown in figure 3 below. figure 3 ? display data read with the insertion of dummy read 7.3 mpu parallel 8080-series interface the parallel interface consists of 8 bi-directional data pins (d 0 - d 7 ), r/w(wr#), e(rd#), d/c and cs#. the cs# input serves as data latch signal (clock) when it is low. whether it is display data or status register read is controlled by d/c. r/w(wr#) and e(rd#) input indicates a write or read cycle when cs is low. refer to figure 12 of parallel timing characteristics for parallel interface timing diagram of 8080-series microprocessor. similar to 6800-series interface, a dummy read is also required before the first actual display data read. r/w (wr ) e(rd ) n n n+1 n+ 2 data bus write column address dum my rea d data read1 data read 2 data read 3
ssd1828 rev 1.10 07/2002 solomon 12 7.4 mpu serial 4-wire interface the serial interface consists of serial clock sck, serial data sda, d/c and cs#. sda is shifted into a 8-bit shift register on every rising edge of sck in the order of d 7 , d 6 , ... d 0 . d/c is sampled on every eighth clock and the data byte in the shift register is written to the display data ram or command register in the same clock. no extra clock or command is required to end the transmission. 7.5 mpu serial 3-wire interface operation is similar to 4-wire serial interface while d/c is not been used. the display data length instruction is used to indicate that a specified number display data byte(s) (1-256) are to be transmitted. next byte after the display data string is handled as a command. it should be noted that if there is a signal glitch at sck that causing an out of synchronization in the serial communication, a hardware reset pulse at res# pin is required to initialize the chip for re-synchronization. table 5 -modes of operation 6800 parallel 8080 parallel serial data read yes yes no data write yes yes yes command read status only status only no command write yes yes yes 7.6 graphic display data ram (gddram) the gddram is a bit mapped static ram holding the bit pattern to be displayed. the size of the ram is 96 x 65 = 6,240bits for ssd1828. figure 5 is a description of the gddram address map. for mechanical flexibility, re-mapping on both segment and common outputs are provided. for vertical scrolling of display, an internal register storing the display start line can be set to control the portion of the ram data mapped to the display. figure 5 shows the case in which the display start line register is set at 30h. for those gddram out of the display common range, they could still be accessed, for either preparation of vertical scrolling data or even for the system usage. 7.7 oscillator circuit this module is an on-chip low power rc oscillator circuitry (figure 4). the oscillator generates the clock for the dc-dc voltage converter. this clock is also used in the display timing generator.
ssd1828 rev 1.10 07/2002 solomon 13 figure 4 - oscillator circuitry 7.8 lcd driving voltage generator and regulator this module generates the lcd voltage needed for display output. it takes a single supply input and generates necessary bias voltages. it consists of: 1. 2x, 3x, 4x and 5x dc-dc voltage converter 2. bias divider if the output op-amp buffer option in set power control register command is enabled, this circuit block will divide the regulator output (v out ) to give the lcd driving levels (v l2 - v l5 ). the divider does not require external capacitors to reduce the external hardware and pin counts. 3. contrast control software control of 64 voltage levels of lcd voltage. 4. bias ratio selection circuitry software control of 1/4 to 1/9 bias ratio to match the characteristic of lcd panel. 5. self adjust temperature compensation circuitry provide 4 different compensation grade selections to satisfy the various liquid crystal temperature grades. the grading can be selected by software control. defaulted temperature coefficient (ptc3) value is -0.05%/c. 7.9 161 bit latch a register carries the display signal information. in 96 x 65 display-mode, data will be fed to the hv-buffer cell and level-shifted to the required level. 7.10 level selector level selector is a control of the display synchronization. display voltage can be separated into two sets and used with different cycles. synchronization is important since it selects the required lcd voltage level to the hv buffer cell, which in turn outputs the com or seg lcd waveform. 7.11 hv buffer cell (level shifter) hv buffer cell works as a level shifter, which translated the low voltage output signal to the required driving voltage. the output is shifted out with an internal frm clock, which comes from the display timing generator. the voltage levels are given by the level selector, which is synchronized with the internal m signal. osc1 oscillator enable internal resistor osc2 buffer enable oscillation circuit enable (cl)
ssd1828 rev 1.10 07/2002 solomon 14 7.12 default value after hardware reset when res input is low, the chip is initialized to the following: register default value remarks: page address 0 column address 0 display on/off 0 display off display start line 0 gddram page 0,d0 display offset 0 com0 is mapped to row0 mux ratio 40h 64 mux normal/reverse display 0 normal display n-line inversion 0 no n-line inversion entire display 0 entire display is off dc-dc booster 3 2x booster is selected internal resistor ratio 0 gain = 2.3 (ir0) contrast 20h lcd bias ratio 5 1/9 bias ratio scan direction of com 0 normal scan direction segment remap 0 segment remap is disabled internal oscillator 0 internal oscillator is off temperature coefficient 2 ptc3 (-0.05%/ o c) icon display 0 icon display line is off frame frequency 2 frame frequency = 75hz power control 0,0,0 booster, regulator & divider are both disabled when reset command is issued, the following parameters are initialized only: register default value remarks: page address 0 column address 0 display start line 0 gddram page 0,d0 internal resistor ratio 0 gain = 2.3 (ir0) contrast 20h 7.13 lcd panel driving waveform the following is an example of how the common and segment drivers may be connected to a lcd panel. the waveforms shown in figure 6and figure 7 illustrate the desired multiplex scheme with n-line inversion feature is disabled (default).
ssd1828 rev 1.10 07/2002 solomon 1 5 normal re-mapped d3 d2 d2 d0 d 0 ???.. 0 0 com16 com47 d 1 ???.. 0 1 com17 com46 d 2 ???.. 0 2 com18 com45 d 3 ???.. 0 3 com19 com44 d 4 ???.. 0 4 com20 com43 d 5 ???.. 0 5 com21 com42 d 6 ???.. 0 6 com22 com41 d 7 ? ??.. 0 7 com23 com40 d 0 ???.. 0 8 com24 com39 d 1 ???.. 0 9 com25 com38 d 2 ???.. 0 a com26 com37 d 3 ???.. 0 b com27 com36 d 4 ???.. 0 c com28 com35 d 5 ???.. 0 d com29 com34 d 6 ???.. 0 e com30 com33 d 7 ???.. 0 f com31 com32 d 0 ???.. 3 0 com0 com63 d 1 ???.. 3 1 com1 com62 d 2 ???.. 3 2 com2 com61 d 3 ???.. 3 3 com3 com60 d 4 ???.. 3 4 com4 com59 d 5 ???.. 3 5 com5 com58 d 6 ???.. 3 6 com6 com57 d 7 ? ??.. 3 7 com7 com56 d 0 ???.. 3 8 com8 com55 d 1 ???.. 3 9 com9 com54 d 2 ???.. 3 a com10 com53 d 3 ???.. 3 b com11 com52 d 4 ???.. 3 c com12 com51 d 5 ???.. 3 d com13 com50 d 6 ???.. 3 e com14 com49 d 7 ? ??.. 3 f com15 com48 page8 0000 d 0 4 0 icons icons seg re-map = 0 seg re-map = 1 seg outputs seg92 seg93 seg94 seg95 seg0 seg1 seg2 seg3 5f 5f 5e 5d 5c 03 02 01 00 03 5c 5d 5e 1 00 01 02 page7 111 ????? ????? page6 1110 ????? 1 ????? ????? ????? ????? ????? page1 000 page address line a ddress page0 0000 figure 5 - ssd1828 graphic display data ram (gddram) address map (with vertical scroll value 30h)
ssd1828 rev 1.10 07/2002 solomon 16 com1 com2 com3 com4 com5 com6 com7 seg 1 seg 2 seg 3 seg 4 com0 seg 0 figure 6 - lcd display example ?0? figure 7 - lcd driving signal from ssd1828 time slot com0 com1 se g0 se g1 m * note : n is the number of multiplex ratio including icon line if it is enabled, n is equal to 64 on por . v out v l5 v l4 v l3 v l2 v ss v out v l5 v l4 v l3 v l2 v ss v out v l5 v l4 v l3 v l2 v ss v out v l5 v l4 v l3 v l2 v ss 123456 78 9 . . . n * 123456 78 9 . . . n * 123456 78 9 . . . n * 12 3456 789 . . . n *
ssd1828 rev 1.10 07/2002 solomon 17 command table table 6 - command table bit pattern command description 0000 c 3 c 2 c 1 c 0 set column lsb set the lower nibble of the column address pointer for ram access. the pointer is reset to 0 after reset. 0001 0c 6 c 5 c 4 set column msb set the upper nibble of the column address pointer for ram access. the pointer is reset to 0 after reset. 0010 0r 2 r 1 r 0 set internal resistor ratio the internal regulator gain (1+r 2 /r 1 ) vout increases as r 2 r 1 r 0 is increased from 000b to 111b. the factor, 1+r 2 /r 1 , is given by: r 2 r 1 r 0 = 000: 2.3 (por) r 2 r 1 r 0 = 001: 3.0 r 2 r 1 r 0 = 010: 3.7 r 2 r 1 r 0 = 011: 4.4 r 2 r 1 r 0 = 100: 5.1 r 2 r 1 r 0 = 101: 5.8 r 2 r 1 r 0 = 110: reserved r 2 r 1 r 0 = 111: reserved (refer to 8.14) 0010 1vc vr vf set voltage control vc vr = 00: turn off the internal voltage booster & regulator (por) vc vr = 01,10,11: turn on the internal voltage booster & regulator vf=0: turn off the output op-amp buffer (por) vf=1: turn on the output op-amp buffer 0011 1t 2 t 1 t 0 set tc value this command set the temperature coefficient t 2 t 1 t 0 : 001: -0.035%/ o c 010: -0.035%/ o c 011: -0.05%/ o c (por) 100: -0.083%/ o c 0100 00xx xl 6 l 5 l 4 l 3 l 2 l 1 l 0 set initial display line the second command specifies the row address pointer (0-63) of the ram data to be displayed in com0. this command has no effect on icons. the pointer is set to 0 after reset. 0100 01xx xxc 5 c 4 c 3 c 2 c 1 c 0 set initial com0 the second command specifies the mapping of first display line (com0) to one of row0~63. this command has no effect on icons. com0 is mapped to row0 after reset.
ssd1828 rev 1.10 07/2002 solomon 18 bit pattern command description 0100 10xx xd 6 d 5 d 4 d 3 d 2 d 1 d 0 set multiplex ratio (partial display) the second command specifies the number of lines, excluding icons, to be displayed. with icon is disabled (por), 16~64 mux could be selected. with icon enabled, the available mux are 17~ 65. d6 ? d0 mux (icon disable) mux (icon enable) 000000 invalid invalid ? 0001111 invalid invalid 0010000 16 17 0010001 17 18 ? 1000000 64 65 1000001 invalid invalid 1000010 invalid invalid ? 1111111 invalid invalid 0100 11xx xxxn 4 n 3 n 2 n 1 n 0 set n-line inversion the second command sets the n-line inversion register from 3 to 33 lines to reduce display crosstalk. register values from 00001b to 11111b are mapped to 3 lines to 33 lines respectively. value 00000b disables the n-line inversion, which is the por value. to avoid a fix polarity at some lines, it should be noted that the total number of mux (including the icon line) should not be a multiple of the lines of inversion (n). 0101 0b 2 b 1 b 0 set lcd bias sets the lcd bias from 1/4 ~ 1/9 according to b 2 b 1 b 0 : 000: 1/4 bias 001: 1/5 bias 010: 1/6 bias 011: 1/7 bias 100: 1/8 bias 101: 1/9 bias (por) 110: 1/9 bias 111: 1/9 bias 0110 01b 1 b 0 set boost level set the dc-dc multiplying factor from 2x to 5x b 1 b 0 : 00: 3x 01: 4x 10: 5x 11: 2x (por) 1000 0001 xxc 5 c 4 c 3 c 2 c 1 c 0 set contrast level the second command sets one of the 64 contrast levels. the darkness increase as the contrast level increase. 1010 000s 0 set segment re-map s 0 =0: column address 00h is mapped to seg0 (por) s 0 =1: column address 5fh is mapped to seg0 1010 001c 0 icon control register on/off c 0 =0: disable icon row (mux = 16 to 64, por) c 0 =1: enable icon row (mux = 17 to 65) 1010 010e 0 entire display select e 0 =0: normal display (display according to ram contents, por) e 0 =1: all pixels are on regardless of the ram contents *note: this command will override the effect of ?set normal/invert display? 1010 011r 0 invert display select r 0 =0: normal display (display according to ram contents, por) r 0 =1: invert display (on and off pixels are inverted) *note: this command will not affect the display of the icon lines
ssd1828 rev 1.10 07/2002 solomon 19 bit pattern command description 1010 1000 nop no operation 1010 1001 power save mode sleep mode: oscillator: off lcd power supply: off com/seg outputs: v ss 1010 1011 start internal oscillator this command starts the internal oscillator. note that the oscillator is off after reset, so this instruction must be executed for initialization 1010 111d 0 display on/off turn the display on and off without modifying the content of the ram. (0: off, 1: on) this command has priority over entire display on/off and invert display on/off. commands are accepted while the display is off, but the visual state of the display does not change. 1011 p 3 p 2 p 1 p 0 set page address set gddram page address (0~8) using p 3 p 2 p 1 p 0 for ram access. the page address is sets to 0 after reset. 1100 s 0 xxx set com scan direction set the com (row) sc anning direction. (0: com0 com63, 1: com63 com0) 1101 1f 2 f 1 f 0 set frame frequency this command is used to set the frame frequency. f 2 f 1 f 0 frame frequency 000 68 001 73 010 75 (por) 011 80 100 80 101 86 110 90 111 100 1110 0001 exit power-save mode dc-dc converter, regulator and divider status before entering the power-save mode is restored. at por, power-save mode is released. 1110 0010 software reset reset some functions of the driver/controller. see reset section below for more details. 1110 0100 release n-line inversion mode release the driver/controller from n-line inversion mode. the frame will be inverted once per frame 1110 1000 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 display data length this command is used in 3-line spi mode (without d/c line) to specify that the controller is about to send display data to the display ram. eight bits are used to specify the number of bytes to be sent (1 to 256 bytes). the second command received after the display data is transmitted is assumed to be command data.
ssd1828 rev 1.10 07/2002 solomon 20 table 7 ? extended command table bit pattern command comment 1111 0010 0000 x 0 000 enable external oscillator input select external oscillator input form cl pin. x 0 = 0 : (por) internal rc oscillator x 0 = 1 : external square wave other than above reserved
ssd1828 rev 1.10 07/2002 solomon 21 7.14 read status byte a 8 bits status byte will be placed to the data bus if a read operation is performed if d/c is low. the status byte is defined as follow. table 8 - read status byte bit pattern command comment busy on res 0 1000 read status busy=0: chip is idle busy=1: chip is executing instruction on=0: display is off on=1: display is on res=0: chip is idle res=1: chip is executing reset 7.15 data read / write to read data from the gddram, input high to r/w(wr#) pin and d/c pin for 6800-series parallel mode. low to e(rd#) pin and high to d/c pin for 8080-series parallel mode. no data read is provided for serial mode. in normal mode, gddram column address pointer will be increased by one automatically after each data read. also, a dummy read is required before the first data is read. see figure 3 in functional description. to write data to the gddram, input low to r/w(wr#) pin and high to d/c pin for 6800-series parallel mode. for serial interface, it will always be in write mode. gddram column address pointer will be increased by one automatically after each data write. the address will be reset to 0 in next data read/write operation is executed when it is 95. table 9 - address increment table d/c r/w (wr) comment address increment 0 0 write command no 0 1 read status no 1 0 write data yes 1 1 read data yes address increment is done automatically after data read/write. the column address pointer of gddram is also affected. it will be reset to 0 in next data read/write operation is executed when it is 95. table 10 - commands required for r/w (wr#) actions on ram r/w (wr) actions on rams commands required read/write data from/to gddram set gddram page address set gddram column address read/write data (1011x 3 x 2 x 1 x 0 )* (0001x 3 x 2 x 1 x 0 )* (0000x 3 x 2 x 1 x 0 )* (x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 ) * no need to resend the command again if it is set previously. the read / write action to the display data ram does not depend on the display mode. this means the user can change the ram content whether the target ram content is being displayed or not.
ssd1828 rev 1.10 07/2002 solomon 22 8 command descriptions 8.1 set display on/off this command turns the display on/off, by the value of the lsb. 8.2 set display start line this command is to set display start line register to determine starting address of display ram to be displayed by selecting a value from 0 to 63. with value equals to 0, d0 of page 0 is mapped to com0. with value equals to 1, d1 of page0 is mapped to com0. the display start line values of 0 to 63 are assigned to page 0 to 7. 8.3 set page address this command positions the page address to 0 to 8 possible positions in gddram. refer to figure 5. 8.4 set higher column address this command specifies the higher nibble of the 7-bit column address of the display data ram. the column address will be incremented by each data access after it is pre-set by the mcu and returning to 0 once overflow (>95). 8.5 set lower column address this command specifies the lower nibble of the 7-bit column address of the display data ram. the column address will be incremented by each data access after it is pre-set by the mcu and returning to 0 once overflow (>95). 8.6 set temperature coefficient (tc) value this command is to set 1 out of 4 different temperature coefficients in order to match various liquid crystal temperature grades. 8.7 set segment re-map this commands changes the mapping between the display data column address and segment driver. it allows flexibility in layout during lcd module assembly. refer to figure 5. 8.8 set normal/reverse display this command sets the display to be either normal/reverse. in normal display, a ram data of 1 indicates an ?on? pixel while in reverse display; a ram data of 0 indicates an ?on? pixel. the icon line is not affected by this command. 8.9 set entire display on/off this command forces the entire display, including the icon row, to be ?on? regardless of the contents of the display data ram. this command has priority over normal/reverse display. to execute this command, set display on command must be sent in advance. 8.10 set lcd bias this command selects a suitable bias ratio (1/4 to 1/9) required for driving the particular lcd panel in use. the por is set to 1/9 bias.
ssd1828 rev 1.10 07/2002 solomon 23 con out v r r v * 1 1 2 ? ? ? ? ? ? ? ? + = ref con v v * 210 63 1 ? ? ? ? ? ? ? ? = 8.11 software reset this command causes some of the internal status of the chip to be initialized: register default value remarks: page address 0 column address 0 display start line 0 gddram page 0,d0 internal resistor ratio 0 gain = 2.3 (ir0) contrast 20h 8.12 set com output scan direction this command sets the scan direction of the com output allowing layout flexibility in lcd module assembly. 8.13 set power control register this command turns on/off the various power circuits associated with the chip. there are three power relating sub-circuits could be turned on/off by this command. internal voltage booster is used to generate the highest positive voltage supply internally from the voltage input (v ci -v ss ). internal regulator is used to generate the lcd driving voltage. output op-amp buffer is the internal divider for dividing the different voltage levels (v l2 , v l3 , v l4 , v l5 ) from the internal regulator output, v out . external voltage sources should be fed into this driver if this circuit is turned off. 8.14 set internal regulator resistors ratio this command is to enable any one of the eight internal resistor (irs) settings for different regulator gains when using internal regulator resistor network. the contrast control voltage range curves is referred to the following formula: where , v vref 1 . 2 =
ssd1828 rev 1.10 07/2002 solomon 24 contrast curve 0 2 4 6 8 10 12 14 16 0 10203040506070 contrast[0~63] v out ir0 ir1 ir2 ir3 ir4 ir5 ir6 ir7 figure 8 - contrast control voltage range curve (v dd =2.775v; v ci =3.5v; tc=-0.05%/ o c) 8.15 set contrast control register this command adjusts the contrast of the lcd panel by changing v out of the lcd drive voltage provided by the on-chip power circuits. v out is set with 64 steps (6-bit) contrast control register. it is a compound commands: figure 9 - contrast control flow set segment re-map changes complete? n o yes set contrast control register contrast level data
ssd1828 rev 1.10 07/2002 solomon 25 8.16 set frame frequency this command specifies the frame frequency so as to minimize the flickering due to the ac main frequency. the frequency is set to 75hz at 64 mux after por. 8.17 set multiplex ratio this command switches default 64 multiplex modes to any multiplex from 16 to 64, if icon is disabled (por). when icon is set enable, the corresponding multiplex ratio setting will be mapped to 17 to 65. the chip pads row0-row63 will be switched to corresponding com signal output as specified in table 2. 8.18 set power save mode force the chip to enter standby or sleep mode. lsb of the command will define which mode will be entered. 8.19 exit power save mode this command releases the chip from sleep mode and return to normal operation. 8.20 set n-line inversion number of line inversion is set by this command for reducing crosstalk noise. 3 to 33-line inversion operations could be selected. at por, this operation is disabled. it should be noted that the total number of mux (including the icon line) should not be a multiple of the inversion number (n). or else, some lines will not change their polarity during frame change. 8.21 exit n-line inversion this command releases the chip from n-line inversion mode. the driving waveform will be inverted once per frame after issuing this command. 8.22 set dc-dc converter factor internal dc-dc converter factor is set by this command. for ssd1828, 2x to 5x multiplying factors could be selected. 2x to 5x factors are selected using this command. 8.23 set icon enable this command enable/disable the icon displays. 8.24 start internal oscillator after por, the internal oscillator is off. it should be turned on by sending this command to the chip. 8.25 set display data length this two-bytes command only valid when 3-wire spi configuration is set by h/w input (ps0=ps1=l). the second 8-bit is used to indicate that a specified number display data byte(s) (1-256) are to be transmitted. next byte after the display data string is handled as a command. 8.26 set test mode this command forces the driver chip into its test mode for internal testing of the chip. under normal operation, user should not use this command.
ssd1828 rev 1.10 07/2002 solomon 26 8.27 status register read this command is issued by setting d/c low during a data read (refer to figure 1 and 2 parallel interface waveform). it allows the mcu to monitor the internal status of the chip. no status read is provided for serial mode. extended commands these commands are used, in addition to basic commands, to trigger the enhanced features, on top of general ones, designed for the chip. 8.28 enable external oscillator input. this command enables the external clock input from cl pin and expected external square wave is 58.5khz.
ssd1828 rev 1.10 07/2002 solomon 27 9 maximum ratings table 11 - maximum ratings (voltage referenced to v ss ) symbol parameter value unit v dd -0.3 to 5.5 v v cc supply voltage v ss -0.3 to v ss +12.0 v v ci booster supply voltage v dd to +5.5 v v in input voltage v ss -0.3 to v dd +0.3 v i current drain per pin excluding v dd and v ss 25 ma t a operating temperature -40 to +85 c t stg storage temperature range -65 to +150 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits in the electrical characteristics tables or pin description section. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. for proper operation it is recommended that v in and v out be constrained to range v ss < or = (v in or v out ) < or = v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g. either v ss or v dd ). unused outputs must be open. this device may be light sensitive. caution should be taken to avoid exposure of this device any light source during normal operation. this device is not radiation protected.
ssd1828 rev 1.10 07/2002 solomon 28 10 dc characteristics table 12 - dc characteristics (unless otherwise specified, voltage referenced to v ss , v dd = 1.8 to 3.3v, t a = -40 to 85 c) symbol parameter test condition min typ max unit v dd logic circuit supply voltage range (absolute value referenced to v ss ) 1.8 2.7 3.3 v v ci booster voltage supply pin (absolute value referenced to v ss ) v dd - 3.6 v i ac access mode supply current drain (v dd pins) v dd = 2.7v, voltage generator on, 4x dc-dc converter enabled, write accessing, t cyc =3.3mhz, osc. freq.=58.5khz, display on. - 600 800 ua i dp1 display mode supply current drain (v dd & v ci pins) v dd =v ci = 2.7v, voltage generator off, external v out divider enable. read/write halt, osc. freq. = 58.5khz, display on, v out = 10.0v. - 20 40 a i dp2 display mode supply current drain (v dd &v ci pins) v dd = 1.8v, v ci = 2.5v, voltage generator on, 5x dc-dc converter enabled, internal v out divider enable. read/write halt, osc freq. = 58.5khz, display on, v out = 10.0v, no panel loading. - 100 150 a i sleep sleep mode supply current drain (vdd pins) v dd = 2.7v, lcd driving waveform off, oscillator off, read/write halt. - 0.5 1 a v out lcd driving voltage generator output (v out pin) display on, voltage generator enabled, dc/dc converter enabled, regulator enabled, osc. freq. = 58.5khz, 4.0 - 12.0 v dc-dc converter efficiency (without loading) - 95 - % v lcd lcd driving voltage input (v out pin) voltage generator disabled 4.0 - 12.0 v v oh1 output high voltage (d 0 -d 7 ) i out = +500a 0.8*v dd - v dd v lcd v ol1 out low voltage (d 0 -d 7 ) i out = -500a 0 - 0.2*v dd v v out lcd driving voltage source (v out pin) regulator enabled (v out voltage depends on internal contrast control) v dd - 12.0 v v out lcd driving voltage source (v out pin) regulator disable - floating - v v ih1 input high voltage (/res, ps0, ps1, /cs, d/c, r/w, d 0 -d 7 ) 0.8*v dd - v dd v v il1 input low voltage (/res, ps0, ps1, /cs, d/c, r/w, d 0 -d 7) 0 - 0.2*v dd v v out lcd display voltage output bias divider enabled, 1:a bias ratio - v out - v v l5 (v out , v l5 , v l4 , v l3 , v l2 pins)\ - (a-1)/a*v out - v v l4 - (a-2)/a*v out - v
ssd1828 rev 1.10 07/2002 solomon 29 symbol parameter test condition min typ max unit v l3 - 2/a* v out - v v l2 - 1/a* v out - v v out lcd display voltage input (v out , v l5 , v l4 , v l3 , v l2 pins) voltage reference to v ss , external voltage generator, bias diver disabled v l5 - v v l5 v l4 - v out v v l4 v l3 - v l5 v v l3 v l2 - v l4 v v l2 v ss v l3 v i oh output high current source (d 0 -d 7 ) output voltage=v dd -0.4v 50 - - a i ol output low current drain (d 0 -d 7 ) output voltage = 0.4v - - -50 a i oz output tri-state current source (d 0 -d 7 ) -1 - 1 a i il /i ih input current (res , ps0, ps1, cs , e, d/c, r/w, d 0 -d 7 -1 - 1 a c in input capacitance (all logic pins) - 5 7.5 pf ? v out variation of vout output (1.8v < v dd < 3.3v) regulator enabled, internal contrast control enabled, set contrast control register = 0 - 1 - % v ref reference voltage (t= 25oc) 2.04 2.1 2.16 v reference voltage (t= - 20oc) 2.09 2.15 2.21 v reference voltage (t= 70oc) 1.99 2.05 2.11 v temperature coefficient compensation ptc1 temperature coefficient 1* voltage regulator enabled 0 -0.01 -0.02 %/ o c ptc2 temperature coefficient 2* voltage regulator enabled -0.025 -0.035 -0.045 %/ o c ptc3 temperature coefficient 3*(por) voltage regulator enabled -0.04 -0.05 -0.06 %/ o c ptc4 temperature coefficient 4* voltage regulator enabled -0.07 -0.083 -0.096 %/ o c * the formula for the temperature coefficient is: tc(%)= x x100% 1 v out at 25oc v out 50oc ? v out at 0oc 50oc ? 0oc
ssd1828 rev 1.10 07/2002 solomon 30 11 ac characteristics table 13 - ac characteristics (unless otherwise specified, voltage referenced to v ss , v dd = v ci = 2.7v, t a = -40 to 85 c) symbol parameter test condition min typ max unit f osc oscillator frequency display on, set 96 x 64 graphic display mode, icon line disabled 50.7 58.5 78 khz f frm frame frequency display on, set 96 x 64 graphic display mode, icon line disabled 65 75 100 hz
ssd1828 rev 1.10 07/2002 solomon 31 table 14 ? parallel timing characteristics (t a = -40 to 85 c, v dd = 1.8v, v ss =0v) symbol parameter min typ max unit t cycle clock cycle time (write cycle) 200 1000 - ns t as address setup time 0 - 25 ns t ah address hold time 0 - - ns t dsw write data setup time 40 - - ns t dhw write data hold time 10 - - ns t dhr read data hold time 10 - 50 ns t oh output disable time - - 40 ns t acc access time (ram) access time (command) 15 15 - - - - ns ns pw csl chip select low pulse width (read ram) chip select low pulse width (read command) chip select low pulse width (write) 500 500 100 - - - - - - ns ns ns pw csh chip select high pulse width (read) chip select high pulse width (write) 200 200 - - - - ns ns t r rise time - - 10 ns t f fall time - - 10 ns valid data t c ycl e t dsw t as t ah t dhr t acc cs d/ c d 0 -d 7 e valid data d 0 -d 7 (write data to driv er) (read data f rom driv er) t dhw pw csl pw csh t f t r r/ w t oh figure 10 ? parallel 6800-series interface timing characteristics (ps0 = h, ps1 = h)
ssd1828 rev 1.10 07/2002 solomon 32 table 15 ? parallel timing characteristics (t a = -40 to 85 c, v dd = 2.7, v ss =0v) symbol parameter min typ max unit t cycle clock cycle time (write cycle) 100 500 - ns t as address setup time 0 - 25 ns t ah address hold time 0 - - ns t dsw write data setup time 30 - - ns t dhw write data hold time 5 - - ns t dhr read data hold time 10 - 50 ns t oh output disable time - - 40 ns t acc access time (ram) access time (command) 15 15 - - - - ns ns pw csl chip select low pulse width (read ram) chip select low pulse width (read command) chip select low pulse width (write) 250 250 50 - - - - - - ns ns ns pw csh chip select high pulse width (read) chip select high pulse width (write) 100 100 - - - - ns ns t r rise time - - 10 ns t f fall time - - 10 ns valid data t c ycl e t dsw t as t ah t dhr t acc cs d/ c d 0 -d 7 e valid data d 0 -d 7 (write data to driv er) (read data f rom driv er) t dhw pw csl pw csh t f t r r/ w t oh figure 11 ? parallel 6800-series interface timing characteristics (ps0 = h, ps1 = h)
ssd1828 rev 1.10 07/2002 solomon 33 table 16 - parallel timing characteristics (t a = -40 to 85 c, v dd = 1.8v, v ss =0v) symbol parameter min typ max unit t cycle clock cycle time (write cycle) 200 1000 - ns t as address setup time 0 - 25 ns t ah address hold time 0 - - ns t dsw write data setup time 40 - - ns t dhw write data hold time 10 - - ns t dhr read data hold time 10 - 50 ns t oh output disable time - - 40 ns t acc access time (ram) access time (command) 15 15 - - - - ns ns pw csl chip select low pulse width (read ram) chip select low pulse width (read command) chip select low pulse width (write) 500 500 100 - - - - - - ns ns ns pw csh chip select high pulse width (read) chip select high pulse width (write) 200 200 - - - - ns ns t r rise time - - 10 ns t f fall time - - 10 ns va lid dat a t cycl e t dsw t as t ah t dhr t ac c cs d/c d 0 -d 7 rd (e) valid data d 0 -d 7 (write dat a to driver) ( re ad d ata from dr iver ) t dhw pw csl pw csh t f t r t oh wr (r/w ) figure 12 - parallel 8080-series interface timing characteristics (ps0 = h, ps1 = l)
ssd1828 rev 1.10 07/2002 solomon 34 table 17 - parallel timing characteristics (t a = -40 to 85 c, v dd = 2.7v, v ss =0v) symbol parameter min typ max unit t cycle clock cycle time (write cycle) 100 500 - ns t as address setup time 0 - 25 ns t ah address hold time 0 - - ns t dsw write data setup time 30 - - ns t dhw write data hold time 5 - - ns t dhr read data hold time 10 - 50 ns t oh output disable time - - 40 ns t acc access time (ram) access time (command) 15 15 - - - - ns ns pw csl chip select low pulse width (read ram) chip select low pulse width (read command) chip select low pulse width (write) 250 250 50 - - - - - - ns ns ns pw csh chip select high pulse width (read) chip select high pulse width (write) 100 100 - - - - ns ns t r rise time - - 10 ns t f fall time - - 10 ns va lid dat a t cycl e t dsw t as t ah t dhr t ac c cs d/c d 0 -d 7 rd (e) valid data d 0 -d 7 (write dat a to driver) ( re ad d ata from dr iver ) t dhw pw csl pw csh t f t r t oh wr (r/w ) figure 13 - parallel 8080-series interface timing characteristics (ps0 = h, ps1 = l)
ssd1828 rev 1.10 07/2002 solomon 35 table 18 ? serial timing characteristics (t a = -40 to 85 c, v dd = 2.7v, v ss =0v) symbol parameter min typ max unit t cycle clock cycle time 58.8 - - ns t as address setup time 10 - - ns t ah address hold time 5 - - ns t css chip select setup time 30 - - ns t csh chip select hold time 29.4 - - ns t dsw write data setup time 30 - - ns t ohw write data hold time 30 - - ns t clkl clock low time 29.4 - - ns t clkh clock high time 29.4 - - ns t r rise time - - 10 ns t f fall time - - 10 ns valid data t cycle t dsw t as t ah sck d/c sda cs t dhw t clkl t clkh t f t r t css t cs h (required if ps1 = h) d7 d6 d5 d4 d3 d2 d1 d0 sck sda cs figure 14- serial timing characteristics (ps0 = l)
ssd1828 rev 1.10 07/2002 solomon 36 table 19 ? serial timing characteristics (t a = -40 to 85 c, v dd = 1.8v, v ss =0v) symbol parameter min typ max unit t cycle clock cycle time 111 - - ns t as address setup time 15 - - ns t ah address hold time 10 - - ns t css chip select setup time 60 - - ns t csh chip select hold time 55.5 - - ns t dsw write data setup time 60 - - ns t ohw write data hold time 60 - - ns t clkl clock low time 55.5 - - ns t clkh clock high time 55.5 - ns t r rise time - - 10 ns t f fall time - - 10 ns valid data t cycle t dsw t as t ah sck d/c sda cs t dhw t clkl t clkh t f t r t css t cs h (required if ps1 = h) d7 d6 d5 d4 d3 d2 d1 d0 sck sda cs figure 15 - serial timing characteristics (ps0 = l)
ssd1828 rev 1.10 07/2002 solomon 37 12 application examples figure 16 - typical application (4-wires spi mode) logic pin connections not specified above: pins connected to v dd : e(#rd), r/w, d 0 ~d 5, ps1 pins connected to v ss : ps0, cv ss, rv ss seg95???????????????????????????seg0 display panel size 96 x 64 + 1 icon line icons com0 : : com10 com11 : : com30 com31 com32 com33 : : : : : com63 icons seg95 ?????????????????.????. seg0 remapped com scan direction [command: c8 remapped com scan direction [command: c8 remapped com scan direction [command: c8] : : : : : com30 com31 : : : : com0 icons sck / cs sda / res v ci v dd ssd1828 ic 64 mux (die face ip) where v dd &v ci =2.775v; c1 = 1uf ~ 2uf c2 = 0.22uf ~ 2.2uf v ss remapped com scan direction [command: c8 : : : : com62 com63 icons : : : : com33 com32 v out c1 c2 d / c
ssd1828 rev 1.10 07/2002 solomon 38 solomon systech reserves the right to make changes without further notice to any products herein. solomon systech makes no warr anty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does solomon systech assu me any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without li mitation consequential or incidental damages. ?typical? parameters can and do vary in different applications. all operating parameters, including ?typica ls? must be validated for each customer application by customer?s technical experts. solomon systech does not convey any license under its patent rights nor the rights of others. solomon systech products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the solom on systech product could create a situation where personal injury or death may occur. should buyer purchase or use solomon systech products for any suc h unintended or unauthorized application, buyer shall indemnify and hold solomon systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any clai m of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that solomon systech was negligent regard ing the design or manufacture of the part.

▲Up To Search▲

Price & Availability of SSD1828Z

	To Download SSD1828Z Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .